Electronic devices having partially elevated source/drain structures and related methods

ABSTRACT

Methods of forming an electronic device may include forming a gate electrode on a semiconductor substrate, and forming first and second impurity doped regions of the semiconductor substrate on opposite sides of the gate electrode. An insulating layer may be formed on the semiconductor substrate including the first and second impurity doped regions, and first and second holes may be formed in the insulating layer, with the first and second holes respectively exposing portions of the first and second impurity doped regions. In addition, first and second epitaxial semiconductor layers may be formed in the respective first and second holes on the exposed portions of the first and second impurity doped regions of the semiconductor substrate. Related devices are also discussed.

CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. non-provisional patent application claims the benefit of andpriority under 35 U.S.C. § 119 to Korean Patent Application 2004-64400filed on Aug. 16, 2004, the disclosure of which is hereby incorporatedherein in its entirety by reference.

FIELD OF THE INVENTION

The present invention relates to semiconductor devices, and moreparticularly to high voltage semiconductor devices and related methods.

BACKGROUND

Semiconductor devices require a suitable operation voltage according tothe characteristics thereof. With continuous advancement in developingdevice technologies to reduce power consumption, internal voltages havebeen reduced. However, there may be a need for devices or logic circuitsoperable at relatively high voltages. Flash memory devices, for example,may need high writing and/or erasing voltages. High voltage transistorsmay thus be integrated into flash memory devices to supply such a highvoltage to a cell array and/or to pump a low voltage up to a highvoltage.

A junction of a high voltage transistor may be formed using an LDD(lightly doped drain) structure or a DDD (double doped drain) structure.There may be limits to manufacturing more highly integrated devicescapable of resisting high voltages using such junction structures. Ifthe depth of a low-concentration diffusion layer is reduced for thepurpose of overcoming a short-channel effect, for example, a junctionbreakdown between a high-concentration diffusion layer and a substratemay result. If a concentration distribution of a high-concentrationdiffusion layer is alleviated to overcome junction breakdown, aneffective area of the high-concentrated diffusion layer may increase.

An elevated source/drain technology has thus been developed with anepitaxial layer being formed on a substrate and impurities beingimplanted into the epitaxial layer. Korean Patent Publication No.2001-109783 and U.S. Pat. No. 6,087,235 disclose methods of fabricatinga transistor with an elevated source/drain structure being formed usingselective epitaxial growth. FIGS. 1 through 3 are cross-sectional viewsillustrating a conventional method of fabricating a transistor.

Referring to FIG. 1, in the conventional transistor, a field isolationfilm 121 is formed in a semiconductor substrate 102 to define an activeregion. A gate insulation layer 302 is formed on the active region, anda conductive gate layer 304 is formed on the gate insulation layer 302.A capping layer 309 is formed on the gate layer 304. A drain diffusionregion 306 and a source diffusion region 308 are formed by implantingimpurities into the semiconductor substrate 102 at opposite sides of thegate layer 304. First spacers 310 are formed at sidewalls of the gatelayer 304. Elevated drain and source contact structures 314 and 316,having a drain facet 318 and a source facet 320 respectively, are formedon the semiconductor substrate 102 beside the first spacers 310.

Referring to FIG. 2, second spacers 330 are formed at both sides of thegate layer 304, covering the source facet 320 and the drain facet 318.The capping layer 309 is etched away from the gate layer 304. Impuritiesare implanted into the elevated drain contact structure 314 and theelevated source contact structure 316. Portions of the substrate 102adjacent to the gate layer 304 may be shielded from the implantedimpurities by the second spacers 330.

Referring to FIG. 3, a drain silicide layer 340 is formed on theelevated drain contact structure 314, a source silicide layer 342 isformed on the elevated source contact structure 316, and a gate silicidelayer 344 is formed on the elevated gate contact structure 304. Aninter-level insulation layer 354 is deposited on the resultant structurefor electrical isolation of components of the transistor 300. Next,drain and source contacts 350 and 352 are formed to provide connectionsto the drain and source silicide layers 340 and 342 passing through theinter-level insulation layer 354.

In the conventional transistor architecture described above, theimpurity implantation is performed to dope the elevated drain contactstructure 314 and the elevated source contact structure 316 to form adrain region and a source region. Accordingly, the source and drainlow-concentration diffusion regions may be shallowly formed on thesubstrate to reduce short-channel effects. Further, since the secondspacers 330 cover the source and drain facets 320 and 318 and thehigh-concentration impurities are implanted into the elevated drain andsource contact structures, an impurity layer may not be formed deeply inlower portions of the source and drain facets 320 and 318. A siliconlayer, however, may be grown with crystallization between the gate layerand the impurity layer. Thus, when a high voltage is applied to thesource contact or the drain contact, an electric field may be exerted onthe silicon layer between the gate layer and the impurity layer. Moreparticularly, when a voltage of 10 to 20 volts or higher is applied tothe source contact or the drain contact, the voltage may be providedthrough the silicon layer to cause an increase of a gate potential. Anincrease of the gate potential due to a source or drain voltage may thusbe reduced by enlarging a thickness of the gate spacer. There may belimits, however, to extending thicknesses of gate spacers in highlyintegrated circuit devices.

SUMMARY OF THE INVENTION

According to some embodiments of the present invention, methods offorming an electronic device may include forming a gate electrode on asemiconductor substrate, and forming first and second impurity dopedregions of the semiconductor substrate on opposite sides of the gateelectrode. An insulating layer may be formed on the semiconductorsubstrate including the first and second impurity doped regions, andfirst and second holes may be formed in the insulating layer. Moreparticularly, the first and second holes may respectively exposeportions of the first and second impurity doped regions. In addition,first and second semiconductor layers may be formed in the respectivefirst and second holes on the exposed portions of the first and secondimpurity doped regions of the semiconductor substrate.

Forming the first and second semiconductor layers may include formingfirst and second epitaxial semiconductor layers, and a crystal structureof the first and second semiconductor layers may be aligned with respectto a crystal structure of the semiconductor substrate. Moreover, formingthe insulating layer may include forming the insulating layer on thegate electrode such that the gate electrode is between the insulatinglayer and the semiconductor substrate. In addition, the first and secondimpurity doped regions of the semiconductor substrate may have impurityconcentrations that are less than impurity concentrations of at leastportions of the respective first and second semiconductor layers.

After forming the first and second semiconductor layers, first andsecond conductive plugs may be formed in the respective first and secondholes on the respective first and second semiconductor layers. Moreparticularly, each of the first and second conductive plugs may includedoped polysilicon. In addition or in an alternative, each of the firstand second conductive plugs may include a metal, and the first andsecond conductive plugs may be in ohmic contact with the respectivefirst and second semiconductor layers.

Before forming the insulating layer, sidewall spacers may be formed onsidewalls of the gate electrode such that a sidewall spacer and portionsof the insulating layer are between the gate electrode and each of thefirst and second semiconductor layers. Moreover, an impurity dopantconcentration of each of the first and second semiconductor layers mayincrease with increasing distance from the semiconductor substrate. Inaddition, a gate insulating layer may be formed such that the gateinsulating layer is between the gate electrode and the semiconductorsubstrate.

According to additional embodiments of the present invention, anelectronic device may include a semiconductor substrate and a gateelectrode on the semiconductor substrate. The first and second impuritydoped regions of the semiconductor substrate may be on opposite sides ofthe gate electrode, and an insulating layer may be on the semiconductorsubstrate including the first and second impurity doped regions. Moreparticularly, the insulating layer may have first and second holestherein respectively exposing portions of the first and second impuritydoped regions. In addition, first and second semiconductor layers may bein the respective first and second holes on the exposed portions of thefirst and second impurity doped regions of the semiconductor substrate.

The first and second semiconductor layers may be first and secondepitaxial semiconductor layers, and the insulating layer may be on thegate electrode such that the gate electrode is between the insulatinglayer and the semiconductor substrate. The first and second impuritydoped regions of the semiconductor substrate may have impurityconcentrations that are less than impurity concentrations of at leastportions of the respective first and second semiconductor layers.

First and second conductive plugs may be provided in the respectivefirst and second holes such that the first and second semiconductorlayers are between the respective first and second conductive plugs andthe first and second impurity doped regions of the semiconductorsubstrate. More particularly, each of the first and second conductiveplugs may include doped polysilicon. In addition or in an alternative,each of the first and second conductive plugs may include a metal, andthe first and second conductive plugs may be in ohmic contact with therespective first and second semiconductor layers.

Sidewall spacers may be provided on sidewalls of the gate electrode suchthat a sidewall spacer and portions of the insulating layer are betweenthe gate electrode and each of the first and second semiconductorlayers. Moreover, an impurity dopant concentration of each of the firstand second semiconductor layers may increase with increasing distancefrom the semiconductor substrate. In addition, a gate insulating layermay be provided between the gate electrode and the semiconductorsubstrate.

According to some embodiments of the present invention, transistorstructures and methods may be provided which reduce short-channeleffects and elevate junction breakdown voltages without increasing anarea of a high-concentration diffusion region. Transistor structures andmethods may also be provided which regulate a potential change of a gateelectrode due to a high voltage applied to a high-concentrationdiffusion region.

According to some embodiments of the present invention, a transistor maybe provided having a partially elevated source/drain structure. Thetransistor may include a gate electrode formed on a semiconductorsubstrate and a low-concentration diffusion region formed in thesemiconductor substrate around both sides of the gate electrode. Aninter-level insulation film may be formed on an entire surface of thesemiconductor substrate on which the gate electrode and thelow-concentrated diffusion region are formed. The inter-level insulationfilm may have contact holes penetrating the low-concentration diffusionregion to reach the semiconductor substrate. An epitaxial layer may beformed on a part of the semiconductor in the contact holes. Ahigh-concentration diffusion region may be formed in the epitaxiallayer. A contact pattern may fill the contact holes on the epitaxiallayer.

The transistor may further include sidewall spacers formed at sidewallsof the gate electrode. Accordingly, the inter-level insulation film maybe sandwiched between the sidewall spacers and the epitaxial layer. Thehigh-concentration diffusion region may extend to the semiconductorsubstrate with a predetermined depth, and its concentration may becomegradually higher away from the low-concentrated diffusion region. Thecontact pattern may be formed of a doped polysilicon or metal pattern.When the contact pattern is formed by metal, the contact pattern and theepitaxial layer may be in ohmic contact with each other.

According to more embodiments of the present invention, methods offabricating a transistor having a partially elevated source/drainstructure may be provided. The method may include forming a gate layeron a semiconductor substrate and implanting low-concentration impuritiesinto the semiconductor substrate around both sides of the gate layer toform a low-concentration diffusion region. An inter-level insulationfilm may be formed on an entire surface of the semiconductor substrateon which the low-concentration diffusion region is formed. Theinter-level insulation film may be patterned to form contact holesexposing the semiconductor substrate on which the low-concentrationdiffusion region is formed. An epitaxial layer may be grown on portionsof the semiconductor substrate exposed by the contact holes.High-concentration impurities may be implanted into the epitaxial layerto form a high-concentration diffusion region. A contact pattern fillingthe contact holes may be formed. During growth of the epitaxial layer,impurities may be implanted with a gradually increasing concentration.The high-concentration diffusion region may extend a predetermined depthinto the semiconductor substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate examples ofembodiments of the present invention and, together with the description,serve to explain principles of the present invention.

FIGS. 1 through 3 are cross-sectional views illustrating a conventionalmethod of fabricating a transistor.

FIG. 4 is a cross-sectional view illustrating transistors according tosome embodiments of the present invention.

FIGS. 5 through 9 are cross-sectional views illustrating steps offabricating transistors according to some embodiments of the presentinvention.

DETAILED DESCRIPTION

The present invention now will be described more fully hereinafter withreference to the accompanying drawings, in which embodiments of theinvention are shown. This invention may, however, be embodied in manydifferent forms and should not be construed as limited to theembodiments set forth herein. Rather, these embodiments are provided sothat this disclosure will be thorough and complete, and will fullyconvey the scope of the invention to those skilled in the art.

In the drawings, the thickness of layers and regions are exaggerated forclarity. It will also be understood that when an element such as alayer, region or substrate is referred to as being on another element,it can be directly on the other element or intervening elements may alsobe present. In contrast, if an element such as a layer, region orsubstrate is referred to as being directly on another element, then noother intervening elements are present. As used herein, the term and/orincludes any and all combinations of one or more of the associatedlisted items.

Furthermore, relative terms, such as beneath, upper, and/or lower may beused herein to describe one element's relationship to another element asillustrated in the figures. It will be understood that relative termsare intended to encompass different orientations of the device inaddition to the orientation depicted in the figures. For example, if thedevice in one of the figures is turned over, elements described as belowother elements would then be oriented above the other elements. Theexemplary term below, can therefore, encompass both an orientation ofabove and, below.

It will be understood that although the terms first and second are usedherein to describe various regions, layers and/or sections, theseregions, layers and/or sections should not be limited by these terms.These terms are only used to distinguish one region, layer or sectionfrom another region, layer or section. Thus, a first region, layer orsection discussed below could be termed a second region, layer orsection, and similarly, a second region, layer or section could betermed a first region, layer or section without departing from theteachings of the present invention. Like numbers refer to like elementsthroughout.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this invention belongs. It will befurther understood that terms, such as those defined in commonly useddictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art andwill not be interpreted in an idealized or overly formal sense unlessexpressly so defined herein.

FIG. 4 is a cross-sectional view illustrating a transistor according tosome embodiments of the present invention. Referring to FIG. 4, a fieldisolation film 52 may be formed on a semiconductor substrate 50 todefine an active region 54. A transistor may be formed at the activeregion 54, and a gate electrode 56 may be formed on the active region54.

Shallow low-concentration impurity doped regions 58 of a depth t1 may beformed in the active region 54 around both sides of the gate electrode56. Sidewall spacers 60 may be formed at sidewalls of the gate electrode56. An epitaxial layer 66 may be selectively grown on a part of eachshallow impurity doped region 58. High-concentration impurity dopedregions 68 may be formed at the epitaxial layer 66. Thehigh-concentration impurity doped regions 68 may extend to apredetermined depth t2 of the semiconductor substrate 50. The epitaxiallayer 66 may be formed in contact holes 64 penetrating inter-levelinsulation film 62 covering the semiconductor substrate 50. Accordingly,portions of the inter-level insulation film 62 separate the epitaxiallayer 66 and the gate electrode 56. When a sidewall spacer 60 is formedat sidewalls of the gate electrode 56, the inter-level insulation film62 may separate the sidewall spacer 60 and the epitaxial layer 66.

Upper portions of the epitaxial layers 66 in the contact holes 64 may befilled with contact patterns 70. Each of the contact patterns 70 may beformed using doped polysilicon and/or a metal. Since the epitaxial layer66 is doped to a higher concentration, the epitaxial layer 66 and amaterial used as the contact pattern 70 may be in ohmic contact with oneanother.

As shown in FIG. 4, parasitic capacitors C1 and C2 are formed betweenthe epitaxial layer 66 and the gate electrode 56. The parasiticcapacitors C1 and C2 may be modeled as serially connected capacitorsusing an inter-level insulation film and a sidewall spacer as dielectricfilms. According to embodiments of the present invention, since aninter-level insulation film is provided between a doped epitaxial layerand a sidewall spacer, elevation of the gate voltage may be reducedbecause of a voltage drop in the inter-level insulation film. Athickness of the sidewall spacer may thus be reduced and/or a separatesidewall spacer may be eliminated to lessen an effective area of thetransistor.

The high-concentration impurity doped region 68 may have a concentrationdistribution that is higher away from a boundary with thelow-concentrated impurity doped region 58. This distribution pattern maybe achieved by forming an epitaxial layer having an impurityconcentration that gradually increases from a lower portion to an upperportion. In other words, since the epitaxial layer 66 may have aconcentration distribution that increases gradually from a lower portionto an upper portion, a concentration of the high-concentration impuritydoped region 68 formed at the epitaxial layer 66 may gradually increasefrom a lower portion to an upper portion. As the high-concentrationimpurity doped region 68 extending to the semiconductor substrate 50comes nearer to the boundary with the low-concentrated impurity dopedregion 58, the concentration thereof may gradually reduce.

FIGS. 5 through 9 are cross-sectional views illustrating steps offabricating a transistor according to embodiments of the presentinvention.

Referring to FIG. 5, field isolation film(s) 52 are formed in asemiconductor substrate 50 to define an active region 54. A gateinsulation layer 51 is formed on the active region 54, and a gateelectrode 56 is formed on the gate insulation layer 51.Low-concentration impurities are implanted into the semiconductorsubstrate 50 at both sides of the gate electrode 56 to formlow-concentration impurity doped regions 58. In addition or in analternative, impurity doped regions 58 may be formed using diffusion. Toreduce extension of the low-concentration impurity doped regions 58 to alower portion of the gate electrode 56, the low-concentration impuritiesmay be shallowly implanted. Additionally, sidewall spacers 60 can beformed at sidewalls of the gate electrode 56.

Referring to FIG. 6, an inter-level insulation film 62 may be formed onan entire surface of the semiconductor substrate 50. The inter-levelinsulation film 62 may be patterned to form contact holes 64 exposingportions of the impurity doped regions 58 of a lower concentration.Epitaxial layers 66 may be formed on portions of the semiconductorsubstrate 50 exposed through contact holes 64. The epitaxial layers 66can be grown using selective epitaxial growth. During growth of theepitaxial layers 66, the epitaxial layers 66 may be doped in situ usingan impurity source during deposition. In addition or in an alternative,the epitaxial layer may be doped using ion implantation and/ordiffusion. During growth of the epitaxial layer 66, the epitaxial layer66 may have an impurity concentration distribution that graduallyincreases from the lower portion to the higher portion. By doing this, ahigh-concentration impurity doped region to be formed later may providea coupling with the low-concentration impurity doped region 58 withoutan abrupt variation of an electric field. Since the epitaxial layers 66may be partially formed in the contact hole 64, a partially elevatedsource/drain structure can be formed on the active region 54.

Referring to FIG. 7, by implanting a high-concentration of impuritiesinto a resulting structure in which the epitaxial layers 66 have beenformed, an impurity doped layer 68 having a relatively highconcentration may be provided at the epitaxial layers 66. Since theepitaxial layers 66 may provide a predetermined depth, boundaries may bedefined in the low-concentration impurity doped regions 58 into whichthe high-concentration impurities may extend. Prior to forming thehigh-concentration impurity doped regions 68, the epitaxial layers 66may be formed with a concentration profile that decreases from upperportions to the lower portions. Thus, the high-concentration impuritydoped regions 68 may also have concentration profiles that decreasegradually from the upper portion of the epitaxial layer 66 to the lowerportion thereof. Even when there has not been any prior doping step forthe epitaxial layer(s), the high-concentration impurity doped region(s)68 formed by an impurity implant and/or diffusion may have aconcentration profile that is lower near the low-concentration diffusionregion(s) 58.

The high-concentration impurity doped region 68 may extend into thesemiconductor substrate 50 a predetermined depth. In this case, thenearer the high-concentration impurity doped regions 68 to thelow-concentration impurity depend region 58, the lower the concentrationthereof. Accordingly, the high-concentration impurity doped regions 68may have a concentration distribution profiles that are higher away fromthe boundary of the low-concentration impurity doped region 58.

Referring to FIG. 8, the contact holes 64 are filled with a conductivefilm to form contact patterns 70 connected to the epitaxial layers 66.The contact patterns 70 may be polysilicon plugs. At this time, thepolysilicon plugs may be in-situ doped or doped by ion implantation. Inan alternative, the contact patterns 70 can be formed of metal.

Referring to FIG. 9, contact holes 64 may be filled with metal to formthe contact patterns 70. The contact patterns 70 may include metalbarrier layers 70 a and metal core layers 70 b. The metal barrier layers70 a may conformally cover inner walls of the contact holes 64 and uppersurfaces of the epitaxial layers 66. The metal barrier layer(s) 70 a maybe a titanium/titanium nitride film(s). The contact holes 64 in whichthe metal barrier layers 70 a are formed may be filled with the metallayer(s) 70 b. The metal layers 70 b may include tungsten, tungstennitride aluminum, and/or copper.

In this case, the contact patterns 70 and the epitaxial layers 66 may bein ohmic contact with each other. The epitaxial layers 66 may be dopedat a higher concentration and a metal silicide may be formed at theboundary between the epitaxial layers 66 and the metal barrier layers 70a allowing the contact patterns 70 and the epitaxial layers 66 to be inohmic contact with each other.

As discussed above, an epitaxial layer is not formed on portions of thesemiconductor substrate exposed at opposite sides of a gate electrodebefore forming an inter-level insulation film. Contact holes exposing apart of the semiconductor substrate may be formed on opposite sides ofthe gate electrode, and the epitaxial layers may be formed on exposedportions of the substrate. Accordingly, the epitaxial layers may beformed at portions of impurity doped regions having a lowerconcentration but the epitaxial layers may be spaced apart from portionsof the substrate in the vicinity of a gate electrode and/or a sidewallspacer.

Such a structure according to embodiments of the present invention mayprovide a potential barrier by an inter-level insulation film separatingthe epitaxial layer(s) and the gate electrode. Accordingly, although ahigh voltage may be applied to the epitaxial layer(s), a voltage dropdue to an inter-level insulation film separating the epitaxial layer(s)and the gate electrode may reduce voltage increases at the gateelectrode.

In addition, since there may be a parasitic capacitor of relatively lowcapacitance between the gate electrode and the epitaxial layer,fluctuations of a gate potential due to electrical signals from thesource and/or drain regions may be reduced.

While the present invention has been particularly shown and describedwith reference to embodiments thereof, it will be understood by thoseskilled in the art that various changes in form and details may be madetherein without departing from the spirit and scope of the invention asdefined by the appended claims and their equivalents.

1. A method of forming an electronic device, the method comprising:forming a gate electrode on a semiconductor substrate; forming first andsecond impurity doped regions of the semiconductor substrate on oppositesides of the gate electrode; forming an insulating layer on thesemiconductor substrate including the first and second impurity dopedregions; forming first and second holes in the insulating layer, thefirst and second holes respectively exposing portions of the first andsecond impurity doped regions; and forming first and second epitaxialsemiconductor layers in the respective first and second holes on theexposed portions of the first and second impurity doped regions of thesemiconductor substrate.
 2. A method according to claim 1 wherein acrystal structure of the first and second epitaxial semiconductor layersis aligned with respect to a crystal structure of the semiconductorsubstrate.
 3. A method according to claim 1 wherein forming theinsulating layer comprises forming the insulating layer on the gateelectrode such that the gate electrode is between the insulating layerand the semiconductor substrate.
 4. A method according to claim 1wherein the first and second impurity doped regions of the semiconductorsubstrate have impurity concentrations that are less than impurityconcentrations of at least portions of the respective first and secondepitaxial semiconductor layers.
 5. A method according to claim 1 furthercomprising: after forming the first and second epitaxial semiconductorlayers, forming first and second conductive plugs in the respectivefirst and second holes on the respective first and second epitaxialsemiconductor layers.
 6. A method according to claim 5 wherein each ofthe first and second conductive plugs comprises doped polysilicon.
 7. Amethod according to claim 5 wherein each of the first and secondconductive plugs comprises a metal.
 8. A method according to claim 7wherein the first and second conductive plugs are in ohmic contact withthe respective first and second epitaxial semiconductor layers.
 9. Amethod according to claim 1 further comprising: before forming theinsulating layer, forming sidewall spacers on sidewalls of the gateelectrode such that a sidewall spacer and portions of the insulatinglayer are between the gate electrode and each of the first and secondepitaxial semiconductor layers.
 10. A method according to claim 1wherein an impurity dopant concentration of each of the first and secondepitaxial semiconductor layers increases with increasing distance fromthe semiconductor substrate.
 11. A method according to claim 1 furthercomprising: forming a gate insulating layer such that the gateinsulating layer is between the gate electrode and the semiconductorsubstrate.
 12. An electronic device comprising: a semiconductorsubstrate; a gate electrode on the semiconductor substrate; first andsecond impurity doped regions of the semiconductor substrate on oppositesides of the gate electrode; an insulating layer on the semiconductorsubstrate including the first and second impurity doped regions, theinsulating layer having first and second holes therein respectivelyexposing portions of the first and second impurity doped regions; andfirst and second epitaxial semiconductor layers in the respective firstand second holes on the exposed portions of the first and secondimpurity doped regions of the semiconductor substrate.
 13. An electronicdevice according to claim 12 wherein the insulating layer is on the gateelectrode such that the gate electrode is between the insulating layerand the semiconductor substrate.
 14. An electronic device according toclaim 12 wherein the first and second impurity doped regions of thesemiconductor substrate have impurity concentrations that are less thanimpurity concentrations of at least portions of the respective first andsecond epitaxial semiconductor layers.
 15. An electronic deviceaccording to claim 12 further comprising: first and second conductiveplugs in the respective first and second holes such that the first andsecond epitaxial semiconductor layers are between the respective firstand second conductive plugs and the first and second impurity dopedregions of the semiconductor substrate.
 16. An electronic deviceaccording to claim 15 wherein each of the first and second conductiveplugs comprises doped polysilicon.
 17. An electronic device according toclaim 15 wherein each of the first and second conductive plugs comprisesa metal.
 18. An electronic device according to claim 17 wherein thefirst and second conductive plugs are in ohmic contact with therespective first and second epitaxial semiconductor layers.
 19. Anelectronic device according to claim 12 further comprising: sidewallspacers on sidewalls of the gate electrode such that a sidewall spacerand portions of the insulating layer are between the gate electrode andeach of the first and second epitaxial semiconductor layers.
 20. Anelectronic device according to claim 12 wherein an impurity dopantconcentration of each of the first and second epitaxial semiconductorlayers increases with increasing distance from the semiconductorsubstrate.
 21. An electronic device according to claim 12 furthercomprising: a gate insulating layer between the gate electrode and thesemiconductor substrate. 22-38. (canceled)